Power device including metal layer

ABSTRACT

A power semiconductor device includes a substrate having an edge, an insulating layer disposed over the substrate, a metal layer disposed over the insulating layer and including a first portion and a second portion, a coating layer disposed over the metal layer, and a protective layer covering the substrate, the insulating layer, the metal layer, and the coating layer. The first portion has a first thickness and the second portion has a second thickness that is greater than the first thickness, and the second portion is disposed farther apart from the edge of the substrate than the first portion.

RELATED APPLICATION

This application is a continuation application of U.S. patentapplication Ser. No. 16/714,249, filed Dec. 13, 2019, which isincorporated by reference herein in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates to a power semiconductor device, inparticular a power device including a metal layer.

BACKGROUND

Power semiconductor devices are used in many different industries. Someof these industries, such as telecommunications, computing and chargingsystems, are rapidly developing.

Power semiconductor devices may have a packaged structure for protectingintegrated circuits (ICs) from physical or chemical attack. For example,such a packaged structure includes a substrate, one or more insulatinglayers, a metal layer, and an encapsulating layer. Mismatch ofcoefficient of thermal expansion (CTE) between constituent materials ofthe packaged structure may induce thermal deformations and stresses,which may deteriorate yield, service life, and reliability of the powersemiconductor devices. For example, tensile stresses may be generated inone or more insulating layers of the packaged structure during amanufacturing process of the power semiconductor devices, leading to anoccurrence of cracks in these insulating layers to reduce the yield ofthe power semiconductor devices.

SUMMARY

Embodiments of the present application relate to a power semiconductordevice including a substrate and a metal layer, where the substrate hasan edge and the metal layer includes a first portion and a secondportion. The second portion is disposed farther apart from the edge ofthe substrate than the first portion. The first portion of the metallayer has a first thickness smaller than a second thickness of thesecond portion, and thereby reducing stresses exerted on the firstportion during a thermal process.

In an embodiment of, a power semiconductor device includes a substratehaving an edge, an insulating layer disposed over the substrate, a metallayer disposed over the insulating layer and including a first portionand a second portion, a coating layer disposed over the metal layer, anda protective layer covering the substrate, the insulating layer, themetal layer, and the coating layer. The first portion has a firstthickness and the second portion has a second thickness that is greaterthan the first thickness, and the second portion is disposed fartherapart from the edge of the substrate than the first portion.

In an embodiment of the above device, the first thickness of the firstportion is in a range from 20% to 60% of the second thickness of thesecond portion.

In an embodiment, a method of forming a power semiconductor deviceincludes forming an insulating layer over a substrate, forming a firstmetal material layer over the insulating layer, forming a second metalmaterial layer over the first metal material layer, etching the secondmetal material layer to form a second metal pattern, and etching thefirst metal material layer to form a first metal pattern. An outer edgeof the second metal pattern is disposed farther than an outer edge ofthe first metal pattern from an edge of the substrate.

In an embodiment, a power semiconductor device includes a substratehaving an edge, a first insulating layer disposed over the substrate, asecond insulating layer disposed over the first insulating layer, ametal layer disposed over the second insulating layer and including afirst portion and a second portion, a passivation layer disposed overthe second insulating layer and the metal layer, a coating layerdisposed over the passivation layer, and a protective layer covering thesubstrate, the first insulating layer, the second insulating layer, themetal layer, the passivation layer, and the coating layer. The firstportion has a first thickness and the second portion has a secondthickness that is greater than the first thickness, and the secondportion is disposed farther apart from the edge of the substrate thanthe first portion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B illustrate a power semiconductor device including ametal layer according to an embodiment.

FIGS. 2A, 2B, 2C, and 2D illustrate a process of forming a powersemiconductor device according to an embodiment.

FIG. 3 illustrates a power semiconductor device including a metal layeraccording to an embodiment.

FIG. 4 illustrates a power semiconductor device including a metal layeraccording to an embodiment.

DETAILED DESCRIPTION

Embodiments of the present application relate to a power semiconductordevice including a substrate and a metal layer. The metal layer includesa first portion and a second portion that is disposed farther apart froman edge of the substrate than the first portion. The first portion ofthe metal layer has a first thickness smaller than a second thickness ofthe second portion, and stresses exerted on the first portion during athermal process may be reduced. For example, the first portion has athickness in a range from 1 μm to 2 μm, and the second portion has athickness in a range from 4 μm to 5 μm. In an embodiment, the firstportion and the second portion form a single integrated body, therebydeforming to absorb a portion of stresses exerted on the metal layer inthe form of elastic energy. A distance between an outer edge of thefirst portion and an outer edge of the second portion is relatively longto further reduce stresses exerted on the second portion during thethermal process. In an embodiment, the metal layer includes a materialhaving relatively high hardness to make the metal layer more resistantto the stresses applied thereon. For example, the metal layer includesan alloy of Al, Cu, and W.

The power semiconductor device further includes a coating layer disposedover the metal layer and a protective layer covering the substrate, themetal layer, and the coating layer. The coating layer has a thicknessthat is relatively thick to reduce the stresses exerted on the metallayer. For example, the thickness of the coating layer is equal to orgreater than 9 μm. The protective layer has one or more materialproperties similar to those of the substrate to reduce stressesgenerated in an upper portion of the power device. For example, theprotective layer has a coefficient of thermal expansion (CTE) that is ina range from 3.4*10⁻⁶/° C. to 8.0*10⁻⁶/° C. whereas a CTE of thesubstrate (e.g., SiC substrate) is in a range from 4.2*10⁻⁶/° C. to4.4*10⁻⁶/° C.

A detailed description of embodiments is provided below along withaccompanying figures. The scope of this disclosure is limited only bythe claims and encompasses numerous alternatives, modifications andequivalents. Although steps of various processes are presented in agiven order, embodiments are not necessarily limited to being performedin the listed order. In some embodiments, certain operations may beperformed simultaneously, in an order other than the described order, ornot performed at all.

Numerous specific details are set forth in the following description.These details are provided to promote a thorough understanding of thescope of this disclosure by way of specific examples, and embodimentsmay be practiced according to the claims without some of these specificdetails. Accordingly, the specific embodiments of this disclosure areillustrative, and are not intended to be exclusive or limiting. For thepurpose of clarity, technical material that is known in the technicalfields related to this disclosure has not been described in detail sothat the disclosure is not unnecessarily obscured.

FIGS. 1A and 1B illustrate a power semiconductor device 100 according toan embodiment of the present disclosure. FIG. 1A is a plan view of thepower semiconductor device 100, and FIG. 1B is a cross-sectional viewalong a line A-A′ of FIG. 1A.

In the embodiment shown in FIGS. 1A and 1B, the power device 100 is apower metal oxide semiconductor field effect transistor (MOSFET) device.For example, such a MOSFET device may have a horizontal channelstructure or a vertical channel structure. In other embodiments, thepower device 100 may be other power devices such as a diode device, aninsulated gate bipolar transistor (IGBT) device, or the like.

The power device 100 includes a semiconductor substrate 102. In anembodiment, the substrate 102 includes a semiconductor compound such asa group IV compound semiconductor substrate, a group III-V compoundsemiconductor substrate, or a group II-VI oxide semiconductor substrate.For example, the substrate 102 includes silicon carbide (SiC) substrate,gallium nitride (GaN) substrate, or gallium arsenide (GaAs) substrate.

A gate dielectric layer (not shown) is disposed between each of one ormore gate electrodes 104 and the semiconductor substrate 102. A firstinsulating layer 106 is disposed over the semiconductor substrate 102and the gate electrodes 104, and includes an oxide or a nitride. Asecond insulating layer 108 is disposed over the first insulating layer106, and includes an oxide or a nitride. The first insulating layer 106and the second insulating layer 108 insulate the gate electrodes 104from a metal layer 110. Although the embodiment shown in FIG. 1Bincludes two insulating layers 106 and 108, embodiments of the presentdisclosure are not limited thereto. For example, a single insulatinglayer (not shown) may replace the first and second insulating layers 106and 108.

The metal layer 110 includes a first portion 110-1 and a second portion110-2. The second portion 110-2 is disposed farther from an edge of thesubstrate 102 than the first portion 110-1. In the embodiment shown inFIG. 1B, an outer edge of the first portion 110-1 is spaced apart fromthe edge of the substrate 102 by a first distance L0 in a horizontaldirection with respect to the orientation of FIG. 1B, and an outer edgeof the second portion 110-2 is spaced apart from the outer edge of thefirst portion 110-1 by a second distance L1 in the horizontal direction.For example, the first distance L0 is equal to or greater than 30 μm,and the second distance L1 is in a range from equal to or greater than20 μm. In addition, the first portion 110-1 has a thickness T1 that issmaller than a thickness T2 of the second portion 110-2. For example,the thickness T1 of the first portion 110-1 may be in a range from 20%to 60% of the thickness T2 of the second portion 110-2, and a leveldifference LD between the thickness T1 of the first portion 110-1 andthe thickness T2 of the second portion 110-2 may be in a range from 40%to 80% of the thickness T2 of the second portion 110-2. In theembodiment shown in FIG. 1B, the thickness T1 of the first portion 110-1is a distance between an upper surface 152 and a lower surface 154 ofthe first portion 110-1 in a vertical direction with respect to theorientation of FIG. 1B. In an embodiment, the lower surface 154 contactsthe top of the barrier layer 114, and the upper surface 152 has asimilar profile to that of the lower surface 154 along the horizontaldirection of FIG. 1B. FIG. 1B shows three thicknesses T1, T1′, and T1″at an outer edge of the first portion 110-1, in an recessed portion ofthe first portion 110-1, and at an inner edge of the first portion110-1, respectively, and these thicknesses T1, T1′, and T1″ of the firstportion 110-1 may be substantially the same. For example, a differencebetween the maximum value and the minimum value among the thicknessesT1, T1′, and T1″ of the first portion 110-1 may be equal to or less than5% of the minimum value. The thickness T2 of the second portion 110-2 isa distance between an upper surface 160 and a lower surface 162 of thesecond portion 110-2. Similarly, the second portion 110-2 hassubstantially the same thickness T2 along the horizontal direction ofFIG. 1B.

The barrier layer 114 is disposed between the metal layer 110 and thesecond insulating layer 108, and serves to substantially block migrationof metal ions from the metal layer 110 to the second insulating layer108, or improve adhesion characteristics of the metal layer 110, orboth. For example, the barrier layer 114 includes Titanium (T1),Titanium nitride (TiN), Tantalum (Ta), or a combination thereof.

Although not shown in the embodiment of FIG. 1B, a conductive layer (notshown) may be disposed between the metal layer 110 and the substrate 102to electrically couple between the metal layer 110 and one or moreportions (e.g., a source region or a drain region) of the substrate 102.For example, such a conductive layer is a silicide layer and includes aplurality of portions each functioning as a source electrode or a drainelectrode. In addition, although not shown in the embodiment of FIG. 1B,an etch stop layer (e.g., an etch stop layer 232′ in FIG. 2D) may bedisposed within the second portion 110-2.

A passivation layer 116 is disposed over the second insulating layer 108and the metal layer 110. In an embodiment, the passivation layer 116includes the same material as that of the first insulating layer 106, orthat of the second insulating layer 108, or both. For example, thepassivation layer 116 includes an oxide or a nitride.

A coating layer 120 is disposed between the passivation layer 116 and aprotective layer 140, and serves to reduce chip stress and substantiallyblock migration of ions from the protective layer 140 to chip circuitryof the power device 100. For example, the coating layer 120 covers thepassivation layer 116 and the first and second portions 110-1 and 110-2of the metal layer 110, and includes polyimide.

The protective layer 140 covers the substrate 102, the first insulatinglayer 106, the second insulating layer 108, the metal layer 110, thepassivation layer 116, and the coating layer 120, and serves to protectthe chip circuitry of the power device 100 from physical or chemicalattack. In an embodiment, the protective layer 140 includes epoxymolding compound (EMC) material, and the EMC material includes silica,epoxy resin, hardener, flame retardant, catalyst, stress relaxationadditive, and the like.

As described above, the power device 100 in FIG. 1B has a packagedstructure to protect the chip circuitry of the power device 100 fromphysical or chemical attack. When a thermal process is performed on sucha packaged structure, thermal deformations and stresses in the powerdevice 100 may be induced, and thus the integrity and reliability of thepackaged structure of the power device 100 may be deteriorated. Forexample, when a cooling process is performed on the protective layer140, the protective layer 140 shrinks to exert compressive stresses on aside surface of the coating layer 120 and exert compressive stresses andshear stresses on a top surface of the coating layer 120. These stressesmay propagate through the coating layer 120 and the propagated stressesmay be exerted on the metal layer 110 to shift the metal layer 110 in aspecific direction (e.g., a right direction with respect to theorientation of FIG. 1B), thereby generating tensile stresses in one ormore of the first insulating layer 106, the second insulating layer 108,and the passivation layer 116. The propagated stresses may also generatea bending moment in a specific direction (e.g., a clockwise directionwith respect to the orientation of FIG. 1B) that pulls a bottom surfaceof the metal layer 110 apart from a top surface of the second insulatinglayer 108. These tensile stresses and bending moment may lead to anoccurrence of cracks in one or more of the first insulating layer 106,the second insulating layer 108, and the passivation layer 116.

When a heating process may be performed on the packaged structure undera reliability test of the power device 100, the substrate 102 has ahigher coefficient of thermal expansion (CTE) than that of each of thefirst insulating layer 106, the second insulating layer 108, and thepassivation layer 116, and thus the substrate 102 expands more thanthese layers 106, 108, and 116. The metal layer 110 also has a higherCTE than that of each of the first insulating layer 106, the secondinsulating layer 108, and the passivation layer 116, and thus the metallayer 110 expands more than the layers 106, 108, and 116. As a result,tensile stresses are generated in one or more of the first insulatinglayer 106, the second insulating layer 108, and the passivation layer116. These tensile stresses may lead to an occurrence of cracks in oneor more of the first insulating layer 106, the second insulating layer108, and the passivation layer 116.

In an embodiment, the coating layer 120 has a thickness T3 that isrelatively thick to reduce the propagated stresses therethrough. Becausethe stresses exerted on the metal layer 110 are reduced, shifting of themetal layer 110 may be reduced and the tensile stresses generated in oneor more of the first insulating layer 106, the second insulating layer108, and the passivation layer 116 may be reduced. The bending moment topull apart the metal layer 110 from the second insulating layer 108 maybe also reduced.

In an embodiment, the thickness T1 of the first portion 110-1 of themetal layer 110 is sufficiently thick to properly serve as an electricalconnection, whereas the thickness T1 of the first portion 110-1 issufficiently thin to minimize a vertical cross-sectional area of thefirst portion 110-1 on which the propagated stresses through the coatinglayer 120 are exerted. For example, the thickness of T1 of the firstportion 110-1 is in a range from 1 μm to 2 μm. Because the first portion110-1 of the metal layer 110 has a relatively thin thickness T1, thevertical cross-sectional area of the first portion 110-1 on which thepropagated stresses are exerted may be reduced, thereby reducing forcesexerted on the vertical cross-sectional area of the first portion 110-1.As a result, shifting of the first portion 110-1 during a thermalprocess may be reduced, thereby reducing the tensile stresses generatedin one or more of the first insulating layer 106, the second insulatinglayer 108, and the passivation layer 116. The bending moment to pullapart the metal layer 110 from the second insulating layer 108 may bealso reduced.

Similarly, the thickness T2 of the second portion 110-2 may besufficiently thin to minimize a vertical cross-sectional area of thesecond portion 110-2 on which the propagated stresses through thecoating layer 120 are exerted. On the other hand, the thickness T2 ofthe second portion 110-2 may be sufficiently large to properly functionas an electric pad when a wire bonding process is performed on thesecond portion 110-2. For example, the thickness of T2 of the secondportion 110-2 is in a range from 4 μm to 5 μm. In addition, the distanceL1 between the outer edge of the first portion 110-1 and the outer edgeof the second portion 110-2 is relatively long to further reduce thestresses exerted on the second portion 110-2. For example, the distanceL1 is equal to or greater than 20 μm. As a result, shifting of thesecond portion 110-2 during a thermal process may be reduced, therebyreducing the tensile stresses generated in one or more of the firstinsulating layer 106, the second insulating layer 108, and thepassivation layer 116. The bending moment to pull apart the metal layer110 from the second insulating layer 108 may be also reduced.

In an embodiment, the first portion 110-1 and the second portion 110-2form a single integrated body, thereby deforming to absorb a portion ofthe stresses exerted thereon in the form of elastic energy. As a result,shifting of the metal layer 110 during a thermal process may be reduced,thereby reducing the tensile stresses generated in one or more of thefirst insulating layer 106, the second insulating layer 108, and thepassivation layer 116. The bending moment to pull apart the metal layer110 from the second insulating layer 108 may be also reduced.

In an embodiment, the protective layer 140 has one or more materialproperties similar to those of the substrate 102. For example, a CTE ofthe protective layer 140 is in a range from 3.4*10⁻⁶/° C. to 8.0*10⁻⁶/°C. whereas a CTE of the substrate 102 is in a range from 4.2*10⁻⁶/° C.to 4.4*10⁻⁶/° C. Because the protective layer 140 has materialproperties similar to those of the substrate 102, stresses generated inan upper portion (e.g., the first insulating layer 106, the secondinsulating layer 108, and the passivation layer 116) of the power device100 due to a difference in the material properties between theprotective layer 140 and the substrate 120 during a thermal process maybe further reduced.

In an embodiment, the metal layer 110 includes a material havingrelatively high hardness. For example, the metal layer 110 includes analloy of Al, Cu, and W that has hardness in a range from 0.63 GPa to0.67 GPa. When the material in the metal layer 110 has relatively highhardness, the material may also have a relatively high elastic modulus.Because the hardness and elastic modulus of a material indicate theresistance to localized plastic deformation and the resistance toelastic deformation of the material, respectively, the metal layer 110may be more resistant to stresses exerted thereon. As a result, shiftingof the metal layer 110 during a thermal process may be reduced, therebyreducing the tensile stresses generated in one or more of the firstinsulating layer 106, the second insulating layer 108, and thepassivation layer 116.

As described above, in the power device 100 according to an embodimentof the present disclosure, the tensile stresses generated in one or moreof the first insulating layer 106, the second insulating layer 108, andthe passivation layer 116 may be reduced. As a result, the tensilestresses generated when a thermal process is performed on the powerdevice 100 may become sufficiently low to substantially prevent anoccurrence of cracks in one or more of the first insulating layer 106,the second insulating layer 108, and the passivation layer 116. Inaddition, the bending moment to pull apart the metal layer 110 from thesecond insulating layer 108 may be reduced, thereby further reducing thelikelihood of such an occurrence of cracks.

FIGS. 2A, 2B, 2C, and 2D illustrate aspects of a method of forming asemiconductor power device (e.g., the power device 100 in FIG. 1)according to an embodiment of this disclosure. More specifically, FIGS.2A-2D illustrate processes of forming a metal layer (e.g., the metallayer 110 in FIGS. 1A and 1B) according to an embodiment. Descriptionson the remaining processes of forming the power device are omittedherein for the interest of brevity.

In FIG. 2A, a first metal material layer 230, an etch stop materiallayer 232, and a second metal material layer 236 are formed over astructure including a substrate 202, one or more gate electrodes 204, afirst insulating layer 206, a second insulating layer 208, and a barriermaterial layer 214. The first and second metal material layers 230 and236 each include a material that is electrically conductive to transmitelectrical signals therethrough. In an embodiment, the material includesaluminum (Al), copper (Cu), tungsten (W), platinum (Pt), tantalum (Ta),silicon (Si), or a combination thereof. For example, each of the firstand second material layers 230 and 236 may include 0.1% Cu, 0.5% W, and99.4% Al, or include 0.5% Cu, 0.8% Si, and 98.7% Al. For example, eachof the first and second metal material layers 230 and 236 may bedeposited using a physical vapor deposition method (e.g., evaporation,DC sputtering, or RF sputtering) or a chemical vapor deposition method(e.g., low-pressure CVD or plasma-enhanced CVD). The first and secondmaterial layers 230 and 236 may be formed such that each of the firstand second material layers 230 and 236 has substantially the samethickness along a horizontal direction with respect to the orientationof FIG. 2A.

The etch stop material layer 232 is formed between the first metalmaterial layer 230 and the second metal material layer 236. In anembodiment, the etch stop material layer 232 includes titanium (T1) ortitanium nitride (TiN). For example, the etch stop material layer 232may be deposited using a physical vapor deposition method (e.g., sputterdeposition, cathodic arc deposition, or electron beam heating) or achemical vapor deposition method. Although not shown in FIG. 2A, aconductive layer may be formed between the first metal material layer230 and the substrate 202 to electrically couple the first metalmaterial layer 230 and one or more portions (e.g., a source region or adrain region) of the substrate 202.

In FIG. 2B, a first mask pattern 250 is formed over the second metalmaterial layer 236, and then a first etching process is performed toform a second metal pattern 236′ using the first mask pattern 250. In anembodiment, a wet etching process is performed on the second metalmaterial layer 236 using the first mask pattern 250 that includes aphotoresist material. An etching rate of the second metal material layer236 is higher than that of the etch stop material layer 232, and thefirst etching process is performed until a portion of the etch stopmaterial layer 232 is exposed.

In FIG. 2C, a second etching process is performed to remove the exposedportion of the etch stop material layer 232, thereby forming an etchstop layer 232′. In an embodiment, a dry etching process is performed onthe exposed portion of the etch stop material layer 232 to form the etchstop layer 232′. Subsequently, a second mask pattern 260 is formed overthe first metal material layer 230 and the second metal pattern 236′.

In FIG. 2D, a third etching process is performed on the first metalmaterial layer 230 to form the first metal pattern 230′ using the secondmask pattern 260. In an embodiment, a wet etching process is performedon the first metal material layer 230 using the second mask pattern 260until a portion of the barrier material layer 214 is exposed.Subsequently, a fourth etching process is performed on the exposedportion of the barrier material layer 214 to remove the exposed portionof the barrier material layer 214, thereby forming a barrier layer 214′.In an embodiment, a dry etching process is performed on the exposedportion of the barrier material layer 214 to form the barrier layer214′. As a result, a metal layer 210 including the first metal pattern230′, the etch stop layer 232′, and the second metal pattern 236′ may beformed. The metal layer 210 may include a first portion that includes anouter portion of the first metal pattern 230′ and has a first thickness(e.g., the first thickness T1 in FIG. 1B). The metal layer 210 mayfurther include a second portion that includes an inner portion of thefirst metal pattern 230′, the etch stop layer 232′, and the second metalpattern 236′ and has a second thickness (e.g., the second thickness T2in FIG. 1B) that is greater than the first thickness.

FIG. 3 illustrate a power semiconductor device 300 according to anembodiment of the present disclosure. The power device 300 includes asemiconductor substrate 302, an insulating layer 308, a passivationlayer 316, a first metal layer 310A, a second metal layer 310B, acoating layer 320, and a protective layer 340. Some elements (e.g., abarrier layer, one or more gate electrodes, a gate dielectric layer, anda silicide layer) of the power device 300 are not shown in FIG. 3 forthe interest of brevity. Although the embodiment shown in FIG. 3includes a single insulating layer 308, embodiments of the presentdisclosure are not limited thereto. For example, the power semiconductordevice 300 may include two or more insulating layers (e.g., the firstand second insulating layers 106 and 108 in FIG. 1B), rather than thesingle insulating layer 308.

The power device 300 includes the first metal layer 310A and the secondmetal layer 310B that are spaced apart from each other by a givendistance. Because the first metal layer 310A and the second metal layer310B are spaced apart from each other, a level difference in an uppersurface of the coating layer 320 may be reduced compared to that when acoating layer (e.g., the coating layer 120 in FIG. 1B) is formed over asingle metal layer (e.g., the metal layer 110 in FIG. 1B) including twoportions (e.g., the first and second portions 110-1 and 110-2 in FIG.1B) coupled to each other. In an embodiment, the first metal layer 310Aand the second metal layer 310B are spaced apart by a distancesufficiently large to minimize a level difference in the upper surfaceof the coating layer 320. For example, a distance L2 between the firstmetal layer 310A and the second metal layer 310B is in a range from 4 μmto 8 μm. In an embodiment, the distance L2 between the first metal layer310A and the second metal layer 310B is about 6 μm, for example, in arange from 5.9 μm to 6.1 μm. As a result, the maximum level differencein the upper surface of the coating layer 320 may be equal to or lessthan 1.5 μm.

Because the level difference in the upper surface of the coating layer320 is relatively small, the stresses exerted on the upper surface ofthe coating layer 320 during a thermal process becomes more uniformcompared to when a relatively large level difference in the uppersurface of the coating layer 320 would lead to stress concentration inthe upper surface. As a result, shifting of the first metal layer 310Aduring a thermal process may be reduced, thereby reducing tensilestresses generated in the insulating layer 308, or the passivation layer316, or both. The bending moment to pull apart the first metal layer310A from the insulating layer 308 may be also reduced. Accordingly, anoccurrence of cracks in the insulating layer 308, or the passivationlayer 316, or both may be substantially prevented in the power device300 according to the embodiment shown in FIG. 3.

FIG. 4 illustrate a power semiconductor device 400 according to anembodiment of the present disclosure. The power device 400 includes asemiconductor substrate 402, an insulating layer 408, a passivationlayer 416, a first metal layer 410A, a second metal layer 410B, acoating layer 420, and a protective layer 440. Some elements (e.g., abarrier layer, one or more gate electrodes, a gate dielectric layer, anda silicide layer) of the power device 400 are not shown in FIG. 4 forthe interest of brevity. Although the embodiment shown in FIG. 4includes a single insulating layer 408, embodiments of the presentdisclosure are not limited thereto. For example, the power semiconductordevice 400 may include two or more insulating layers (e.g., the firstand second insulating layers 106 and 108 in FIG. 1B), rather than thesingle insulating layer 408.

The coating layer 420 includes a plurality of vertical portions that arespaced apart from each other. In an embodiment, the coating layer 420has a honeycomb structure including an array of hollow cells formedbetween adjacent vertical portions. For example, each of the hollowcells may have a specific cross-section (e.g., a hexagon, a square, or arectangle) when seen in a top view and extend in a directionperpendicular to that cross-section. The protective layer 440 fills ahollow cell between adjacent vertical portions of the coating layer 420.

In an embodiment, a distance L3 between adjacent vertical portions ofthe coating layer 420 is in a range from 20 μm to 40 μm. Because theseadjacent vertical portions of the coating layer 420 are spaced apartfrom each other, the coating layer 420 may effectively absorb stressesexerted by the protective layer 440 during a thermal process. As aresult, a thickness T4 of each of the plurality of portions of thecoating layer 420 may be reduced compared to that (e.g., the thicknessT3 in FIG. 1B) of a coating layer (e.g., the coating layer 120 in FIG.1B) without including one or more hollow cells. For example, thethickness T4 of each of the plurality of vertical portions of thecoating layer 420 is in a range from 6 μm to 9 μm.

Aspects of the present disclosure have been described in conjunctionwith the specific embodiments thereof that are proposed as examples.Numerous alternatives, modifications, and variations to the embodimentsas set forth herein may be made without departing from the scope of theclaims set forth below. Accordingly, embodiments as set forth herein areintended to be illustrative and not limiting.

1.-21. (canceled)
 22. A power semiconductor device, comprising: asubstrate having an edge; an insulating layer disposed over thesubstrate; a metal layer disposed over the insulating layer andincluding a first portion and a second portion, the first portion havinga first thickness and the second portion having a second thicknessgreater than the first thickness; a coating layer disposed over themetal layer and having a third thickness greater than the secondthickness, the first portion of the metal layer being disposed betweenthe edge of the substrate and the second portion of the metal layer; anda protective layer covering the substrate, the insulating layer, themetal layer, and the coating layer.
 23. The power semiconductor deviceof claim 22, wherein the first thickness of the first portion is in arange from 20% to 60% of the second thickness of the second portion. 24.The power semiconductor device of claim 22, wherein the first thicknessof the first portion is in a range from 1 μm to 2 μm, and the secondthickness of the second portion is at least 2 μm.
 25. The powersemiconductor device of claim 22, wherein the first thickness is adistance between an upper surface of the first portion and a lowersurface of the first portion at an outer edge of the first portion, andthe second thickness is a distance between an upper surface of thesecond portion and a lower surface of the second portion at an outeredge of the second portion.
 26. The power semiconductor device of claim22, wherein the first portion and the second portion form a singleintegrated body.
 27. The power semiconductor device of claim 22, whereina distance between an outer edge of the first portion and an outer edgeof the second portion is equal to or greater than 20 μm.
 28. The powersemiconductor device of claim 22, wherein the first portion is spacedapart from the second portion by a distance in a range from 4 μm to 8μm.
 29. The power semiconductor device of claim 22, wherein the metallayer includes Al, Cu, and W.
 30. The power semiconductor device ofclaim 22, wherein the third thickness of the coating layer is greaterthan 9 μm.
 31. The power semiconductor device of claim 22, wherein thecoating layer includes a plurality of portions, an adjacent pair of theplurality of portions being spaced apart by a distance in a range from20 μm to 40 μm.
 32. The power semiconductor device of claim 22, whereinthe coating layer has a honeycomb structure.
 33. The power semiconductordevice of claim 22, wherein the third thickness of the coating layer isat least 2 times greater than the second thickness of the secondportion.
 34. The power semiconductor device of claim 22, wherein theprotective layer has a coefficient of thermal expansion (CTE) in a rangefrom 3.4*10⁻⁶/° C. to 8.0*10⁻⁶/° C., and the substrate has a CTE in arange from 4.2*10⁻⁶/° C. to 4.4*10⁻⁶/° C.
 35. The power semiconductordevice of claim 22, wherein the insulating layer is a first insulatinglayer, the power semiconductor device comprising: a second insulatinglayer disposed between the substrate and the first insulating layer; anda passivation layer disposed over the first insulating layer and themetal layer.
 36. The power semiconductor device of claim 22, wherein thesubstrate is silicon carbide (SiC) substrate, Gallium nitride (GaN)substrate, or Gallium arsenide (GaAs) substrate.
 37. A powersemiconductor device, comprising: a substrate having an edge; a firstinsulating layer disposed over the substrate; a second insulating layerdisposed over the first insulating layer; a metal layer disposed overthe second insulating layer and including a first portion and a secondportion, the first portion having a first thickness and the secondportion having a second thickness greater than the first thickness; apassivation layer disposed over the second insulating layer and themetal layer; a coating layer disposed over the passivation layer andhaving a third thickness greater than the second thickness, the firstportion of the metal layer being disposed between the edge of thesubstrate and the second portion of the metal layer; and a protectivelayer covering the substrate, the first insulating layer, the secondinsulating layer, the metal layer, the passivation layer, and thecoating layer.
 38. The power semiconductor device of claim 37, whereinthe first thickness of the first portion is in a range from 20% to 60%of the second thickness of the second portion.
 39. A power semiconductordevice, comprising: a substrate having an edge; an insulating layerdisposed over the substrate; a metal layer disposed over the insulatinglayer and including a first portion and a second portion, the firstportion having a first thickness and the second portion having a secondthickness greater than the first thickness, the second portion beingspaced apart from the first portion; a coating layer disposed over themetal layer and having a third thickness greater than the secondthickness, the first portion of the metal layer being disposed betweenthe edge of the substrate and the second portion of the metal layer; anda protective layer covering the substrate, the insulating layer, themetal layer, and the coating layer.
 40. The power semiconductor deviceof claim 39, wherein the second thickness of the second portion is atleast 2 μm.
 41. The power semiconductor device of claim 39, wherein thethird thickness of the coating layer is greater than 9 μm.
 42. The powersemiconductor device of claim 39, wherein the coating layer includes aplurality of portions that are spaced apart.